| 摘要 |
PURPOSE:To shorten pull-in time without deteriorating a noise band width by resetting an up down counter, a variable frequency-divider and a frequency- divider to be in a lock phase state when the phase difference of a PLL input and an output clock is more than pi/2. CONSTITUTION:When the phase difference of the PLL output clock 11 and the input clock 6 becomes more than pi/2, the output signal of a terminal Q in DFF13 falls from an H level to an L level. The changing time is delayed by a pi/2 phase delay circuit 14, and a a fall change detection circuit 15 resets the up down counter 2a, the frequency ratio variable divider 3a and the frequency-divider 4a. Consequently, the up down counter 2a, the frequency- division rate variable divider 3a, the frequency-divider 4a can be led in the lock phase from when the phase difference of the PLL output clock 11 and the input clock 6 is within pi/2. Consequently, the pull-in time can be shortened. |
