发明名称 HIGH SPEED SYNCHRONOUS PLL OSCILLATOR
摘要 PURPOSE:To allow a control voltage required for a VCO just after the changeover of the number of frequency divisions of a variable frequency divider and to minimize the deviation of an oscillated frequency of the VCO with respect to the change in the oscillated frequency by charging the control voltage of the VCO to one of 1st and 2nd capacitors in response to the number of frequency divisions after the changeover, so as to switch the frequency division ratio of the variable frequency divider. CONSTITUTION:The 1st capacitor 8a is connected to a control loop via a switch 9a before a frequency division ratio designating device 5 is subject to change operation. When a new data is sent to a variable frequency divider 2 by the frequency division ratio designating device 5, the variable frequency divider 2 starts frequency division newly. A switching trigger signal 11 is sent to a switch controller 10 together with the data in this case to change over switches 9a, 9b by using switching signals 12a, 12b. Thus, the 2nd capacitor 8b corresponding to the data is connected to the control loop via the switch 9b to set the controlled voltage of the VCO 1 momentarily and the time required for synchronization is reduced.
申请公布号 JPH01261026(A) 申请公布日期 1989.10.18
申请号 JP19880089981 申请日期 1988.04.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YANASE AKINORI;TAGUCHI KOICHI;KATAYAMA YOSHIO
分类号 H03L7/107;H03L7/10 主分类号 H03L7/107
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