Cache memory controller associated with a microprocessor.

摘要

A cache memory controllor (1) according to the present invention sequentially checks into a controlling circuit ((11) to see whether or not data words accessed are memorized in a cache memory and has a combination of an address generating circuit (12) and a strobe signal producing circuit (14) for producing a plurality of strobe signals (STO to ST3) in the presence of a request signal (BREQ) for a burst transmision mode of operation, so that a microprocessor sequentially fetches the data words in the cache memory even if the cache memory does not cope with the nibble mode of operation.