SPEED VARIABLE DATA COMMUNICATION SYSTEM

摘要

PURPOSE:To allow the system to follow up a clock signal sent from the equipment by detecting a data quantity stored in a buffer memory for each prescribed period by a data quantity detection circuit and switching the clock at a corresponding speed in a timing not giving any effect on the data and sending it. CONSTITUTION:A data quantity detection section 5 counts number of R-CK inputted by an R counter for a prescribed period, a W counter counts number of clocks sent continuously to a terminal equipment B via a clock selection section 61 and the counts of the R and W counters are compared by a comparator. A clock generating section 63 generates plural clocks having a different speed and sends it to a clock selection section 61 and the information of clock is sent to a clock switching timing generating section 62. The clock selection means switches the clock having a speed corresponding to the inputted state signal in the switching timing and sends it to the terminal equipment B as a sent clock. Thus, the terminal equipment B can follow the clock supplied from the terminal equipment A.