发明名称 PLA CONTROL SYSTEM
摘要 PURPOSE:To reduce the current consumption by dividing a PLA(programmable logic array) into plural sub PLAs in response to the function, and applying control so as to bring only a selected sub PLA into the operating state. CONSTITUTION:Plural sub PLAs 51-5n are divisions of the PLA by functions. A clock pulse CLK is supplied to each of clock control circuits 71-7n. Moreover, an input data selecting n-kind of functions, e. g., in order is supplied to each of decoders 61-6n. Each of the decoders 61-6n outputs a signal to the clock control circuits 71-7n respectively only when an input data representing a preset function is inputted to make the input clock pulse CLK effective. Thus, a corresponding clock pulse among the clocks CLK1-CLKn only at the selection of the setting function by the input data is supplied to the sub PLAs 51-5n to apply the operation of precharge/discharge and the remaining sub PLAs not selected are all in precharge state.
申请公布号 JPH01260924(A) 申请公布日期 1989.10.18
申请号 JP19880088592 申请日期 1988.04.11
申请人 FUJITSU LTD;FUJITSU MICROCOMPUTER SYST LTD 发明人 TANIAI KOKICHI;SAITO TADASHI;TANAKA YASUHIRO
分类号 G06F7/00;G06F1/04;H03K19/00;H03K19/177 主分类号 G06F7/00
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