| 摘要 |
PURPOSE:To control a printer efficiently with a small number of memories provided and enable a plurality of printers to be easily driven in parallel by imparting a printer deflection synchronizing signal and a line synchronizing signal from external equipment. CONSTITUTION:FIFO1 is employed as a high-speed I/O buffer between a printer and external equipment, and FIFO1 performs simultaneous write and read processing. The input side of FIFO1 increments write addresses using an image clook(WCLK) and writes the write addresses into a memory. A write address pointer 14 is reset by a horizontal synchronizing signal(WLSYNC) connected from the external equipment 502. The output side reads while incrementing read addresses from the memory cell in which the address data is already written, using RCLK from the printer 501 side. If a horizontal synchronizing signal(RLSYNC) obtained from a rotating polygonal mirror of the printer 501 is connected, a read address pointer 15 is reset to 0. Consequently, image data is correctly written, even if there is a phase offset between WLSYNC and RLSYNC.
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