| 摘要 |
PURPOSE:To enable hardcopies not adversely affected by jitters even if they are based on whatever types of image signals to be obtained by providing an A/D converter, a storage element which stores digital data, a timing signal generating circuit which generates a timing signal for the reception of data from the storage element, a PLL circuit which controls a clock as a reference device, and a delay circuit which matches sampling phases. CONSTITUTION:A sampling clock is generated by a PLL circuit to ensure correct synchronization with a horizontal synchronization. A delay circuit for matching phases is arranged behind a VCO transmitter so that the PLL stability is not affected by the variation in the amount of delay. In addition, a reference signal for the generation of a timing signal which generates a position from a horizontal synchronization period is extracted from a point P after frequency division by N. Also, a clock reference for the generation of a timing signal is extracted from a point Q after delay. |
