发明名称 CLOCK CROSSOVER CIRCUIT
摘要 PURPOSE:To obtain a difference in the crossover timing by blocking the passing in the presence of an abnormality in the period of a load pulse and using an AND so as to gate a pulse whose count period is made coincident and an output of a NAND. CONSTITUTION:A load pulse M to be inputted is NANDed by an E pulse at a NAND 1 to block the passing in the presence of the abnormality in the period of the load pulse M. Moreover, the period is made coincident with the count period of an F pulse and the F pulse and an output of the NAND 1 are ANDed by an AND 2. As a result, a b-adic counter 3 is loaded by the load pulse M when the clock crossover is normal and the counter is loaded by the F pulse when the clock crossover is abnormal. Thus, the crossover function of the two clock frequencies different from each other is realized by a minimum circuit constitution.
申请公布号 JPH01256222(A) 申请公布日期 1989.10.12
申请号 JP19880084456 申请日期 1988.04.05
申请人 FUJITSU LTD 发明人 HAZAMA HISAMICHI
分类号 H03L7/00;G06F1/04;G06F1/08;H03K21/00;H03K23/66;H03L7/06;H04L7/00 主分类号 H03L7/00
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