| 摘要 |
PURPOSE:To obtain an arithmetic processing unit with high total performance by setting a multiplier and a divider as arithmetic elements to perform an arithmetic processing in SD display in which redundancy exists as an internal logic, and providing a data memory with a multi-port. CONSTITUTION:The multiplier 3 and the divider 4 are apparatuses to perform the arithmetic processing by using the SD display in which the redundancy exists as the internal logic, and they can perform the arithmetic processing in around 30 steps and around 120 steps, respectively, and a cycle ratio required for that processing is set at about 1:5. Also, the data memory 1 with the multi- port is provided as an internal register so as to perform a parallel processing by them. A device clock constituted in such way is set at 50ns. Here, when the divider 4 is executing the arithmetic processing and the queue of an instruction is filled, no arithmetic instruction is received by another arithmetic element, however, one of the matrices becomes vacant after five cycles at latest, and the arithmetic instruction can be received by using the matrix, then, the parallel processing with the divider 4 can be performed. Therefore, it is possible to improve the total performance of the device by using a fast clock. |
