| 摘要 |
PURPOSE:To supply a signal holding an L-level or an H-level to an inside circuit even in the setting period for a test mode by supplying a high voltage detecting signal to the inside circuit, for the high voltage of a test mode setting signal in the input signals of a logic circuit IC. CONSTITUTION:By a detecting circuit 1, the high voltage detecting signal HV0 is supplied to the inside circuit corresponding to the high voltage of the test mode setting signal HV in the input signals Ai which are supplied to an input terminal Ti on the logic circuit IC. By a three-state buffer circuit 2, the signals Ai and an output interrupting signal -HV0 caused by the signal HV0 are inputted, and a detecting signal A0 corresponding to the H-level signal lower than the high voltage or the L-level signal in the signals Ai is supplied to an output terminal T0 which is connected to the other inside circuit during the signal HV is not being inputted. Further by a three-state latching circuit 3, the detecting signal A0 is inputted and an internal latching signal Lth is generated every time when a chip-enable signal - CE is received, and by receiving the signal HV0, the signal Lth is supplied to the output terminal T0 only during the signal HV is being inputted. |
