| 摘要 |
PURPOSE:To reduce soft wear errors by a method wherein a grounding line is arranged so as to cover the gate wiring of an MOS transistor constituting FF of a memory cell. CONSTITUTION:The memory cell is formed of a semiconductor substrate 1, an impurity diffused layer 2, isolation regions 3, etc. A word line WL and a power source line Vcc run in a line direction, and the gate wirings G3 and G4 of the cross-bound MOS transistors Q3 and Q4 are formed via an insulation layer 4. The grounding line GND' is formed wide with a conduction width different from that of a bit pair BL, and runs in a line direction. Since the line GND' covers the gate wirings G3 and G4, the amount of charge accumulation increases. |
