Semiconductor devices having multi-level metal interconnects.

摘要

A self-aligned, self-planarized metallization scheme for multilevel interconnections using self-aligned windows in integrated circuits is described. Trenches are etched into a dielectric (27) and then, using an etch stop layer (29) on top of the dielectric (27) to prevent unwanted etching of the dielectric, self-aligned windows which expose portions of the substrate (21) are etched in the dielectric (23). Self-aligned windows can also be formed without a mask.