Circuit arrangement for averaging in the pulse density D/A or A/D conversion.

摘要

In the pulse density D/A or A/D conversion, an improved averaging of a PDM signal (pm) in a jittering clock signal (cl) is achieved by the fact that the PDM signal (pm) is supplied to the series input (zs) of an n-stage shift register (sr), the parallel output (z1, ...zn) of which is used for controlling n state signals (i4....;ii'....; i8....; i8d), the shift register (sr) being switched by the clock signal (cl). The n state signals are combined to form a sum signal (i4s; i6s; i8s; si, siq) which feeds a low-pass filter (tp). Particularly advantageous developments are obtained if the n state signals are weighted and/or isolated from the respective preceding and subsequent state in time by means of gate circuits (g; g, gs).