| 摘要 |
<p>Flip-flop (40) for dividing by 2 the frequency of a signal applied to an input terminal (CK), comprising an RS flip-flop (60) consisting of a first (61) and a second (62) logic gate whose first inputs are mutually intercoupled to their outputs (O1, O2). According to the invention, the flip-flop (40) also comprises a third (20a) and a fourth (20b) logic gate whose outputs (Oa, Ob) are coupled, respectively, to the inputs (I1, I2) of the first (61) and the second (62) logic gate, and whose first inputs are coupled, respectively, to the output (O2, O1) of the second (62) and of the first (61) logic gate, via, respectively, a conduction path of a first (30a) and of a second (30b) interrupter, the second inputs of the third (20a) and of the fourth (20b) logic gate and the input (Ga, Gb) of the interrupters (30a, 30b) being connected to the said input terminal (CK).
<??>Application to LSI digital integrated circuits.
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