| 摘要 |
PURPOSE:To obtain an arithmetic processing unit in which multiplication type division can be accelerated and high total performance can be obtained by providing a subtraction circuit between the output part of a multiplier having SD display in which redundancy in an internal logic and a first register. CONSTITUTION:The multiplier 3 is the one provided with the SD display in which the redundancy exists in the internal logic, and division is executed by performing the multiplication type division to multiply data in a data memory 1 by the inverse of a divisor outputted from a ROM 4. The subtraction circuit 5 required for that division is provided between the output part of the multiplier 3 and a register 11. In the multiplier 3 and the circuit 5, the SD display in which the redundancy exists in the internal logic is used, however, a redundant binary/binary conversion circuit 6 is provided to send processed data to the memory 1. Thereby, multiplication and a processing to subtract the result from '2' can be performed in one cycle, and the division can be performed in a processing time where the cycle of a repetitive multiplication can be reduced by one cycle. In other words, it is possible to decrease the ratio of the processing time of addition and subtraction to the division, and to heighten the total performance as the device. |
