发明名称 ARITHMETIC UNIT
摘要 PURPOSE:To compose the arithmetic unit of minimum circuits by repeating addition and subtraction according to the shift quantity of an input and obtaining an optional coefficient value. CONSTITUTION:This unit consists of a shifter 11 which shifts an input signal, an arithmetic circuit 12 which performs arithmetic operation with the output of the shifter 11 and an output signal, a multiplexer 13 which selects an initial value with the output of the arithmetic circuit 12 and the output signal, and a register 14 which holds the output of the multiplexer 13 for a unit time. Then the shifter 11 operates in such a direction that the power of 2 is obtained and addition or subtraction is carried out only when a necessary shift quantity is obtained during the period and the arithmetic value is stored in the register 14. Then a shifter 11 operates in such a direction that one over the power of 2 is obtained, and addition or subtraction is performed by a necessary quantity to obtain a desired coefficient value. Consequently, the optional coefficient values are obtained without entailing an increase in circuit area.
申请公布号 JPH01253028(A) 申请公布日期 1989.10.09
申请号 JP19880080882 申请日期 1988.03.31
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 FUJII KUNIHIKO;SUZUKI SHIGETO
分类号 G06F7/53;G06F7/52;G06F7/523 主分类号 G06F7/53
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