| 摘要 |
PURPOSE:To shorten delay time and to control the number of steps by making the state of a specific step number control transfer gate selected by a step number control signal into an opened state, transferring input data from a specific transfer step to an output part, and outputting the input data. CONSTITUTION:The title system is equipped with a data transfer part, in which plural series of the transfer steps to transfer the input data are connected, and the input data are delayed and outputted from the output part, and step number control transfer gates 41, 43, 45, and 47, the opening and closing of the gates is controlled by the step number control signal, and the gates are connected to the respective transfer steps. The state of the specific step number control transfer gate selected by the step number control signal is made into the opened state, and the input data are outputted from the output part. Thus, since the input data are sent through the step number control gates 41, 43, 45, and 47 to transfer data lines 70-81 of a shift register, only the driving capacity of a driver for the input data is to be heightened, it is unnecessary to make the sizes of transistors for the respective transfer steps larger, and the number of the steps can be controlled with short delay time. |
