| 摘要 |
<p>The disclosure is directed to a serial in, serial out data shifter. Generally, the data shifter comprises a latch based design (L1-L4) with a four phase clock system (CLK1-CLK4). The latches (L1-L4) are coupled in series and the four phases of the clock (CLK1-CLK4) are coupled to the clock ports of the latches in a predetermined order whereby only four latches are needed to shift and temporarily store three bits of data.</p> |
