| 摘要 |
A digital data processing system including an Instruction Unit 10, an Execute Unit 26, and a multilevel Processor Storage System 12 including a cache memory, further includes a Load Control Block Address Unit 20 for implementing a load control block address instruction which permits prefetching of data from main memory into cache simultaneously with execution of a sequence of instructions in a linked list. Information determining the starting address of a next block in the linked list is stored at a location in the current block at a fixed offset from the beginning of the block. |
