SYNCHRONIZING CIRCUIT

摘要

Synchronizing circuit including a variable delay circuit (DLC) through which an input signal (DIN) is passed to adjust the phase of a regenerated output signal (DIN1) with respect to a clock signal (CL1) at the frequency of the input signal, and a decision circuit (DC) to adjust the variable delay (DL1/8) so that it covers half a period of the input signal and after having detected a predetermined lack of synchronism modifies the value of the variable delay such that this delay may then be adjusted to cover the second half of the period.