| 摘要 |
<p>A first AND gate (18) logically operates a pulse signal which defines a predetermined period for phase comparison and is output from a second counter (30), a first pulse signal which has the same frequency as that of a horizontal sync signal (HS) and is output from a first counter (14), and a second pulse signal which has substantially the same pulse width as that of the first pulse signal and is output from an RS flip-flop (36), to produce thereby a third pulse signal. Only when the first pulse signal advances in phase with respect to the second pulse signal, the pulse width of the third pulse signal depends on the phase difference between them. A second AND gate (20) logically operates the pulse signal output from the second counter (30), and the inverted signals of the first and second pulse signals, thereby producing a fourth pulse signal. Only when the first pulse signal lags in phase with respect to the second pulse signal, the pulse width of the third pulse signal depends on the phase difference between them. Only when receiving either of the third and fourth pulse signals, a switch circuit (22) connects a filter (24) providing a control voltage to a VCO (12) between both ends thereof to a first or second constant current source (26 or 28), thereby charging or discharging the filter (24).</p> |
