发明名称 MULTI LEVEL DIGITAL DATA DECORDING CIRCUIT
摘要 The circuit for communicating a number of information signal through the limited number of channel by extracting none-returnto-zero (NRZ) signal from the transmitted multilevel digital data comprises a horizontal synchronous signal separator (1), pulse generators (2,3) for extracting the colour synchronous signal and the clock run-in signal, switching circuits (4,5), low pass filters (6,7), differential amplifiers (8-10), a decoder (11), AND gates (12-14), mono/muties (15-17), a clock generator (18), and pulse generators (12'-14').
申请公布号 KR890003768(B1) 申请公布日期 1989.10.04
申请号 KR19860008246 申请日期 1986.09.30
申请人 GOLDSTAR CO.,LTD. 发明人 IN, WOONG-SIK
分类号 H04N7/00;(IPC1-7):H04N5/44 主分类号 H04N7/00
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