Arithmetic-logic operation unit having high-order and low-order processing sections and selectors for control of carry flag transfer therebetween

摘要

Two arithmetic logic units (ALUs) are provided, one a high-order side and another on a low-order side such that data on the high-order side and on low-order side, output from each of a source data register and a destination data register, are respectively supplied to the ALUs to be operated on thereby. There is provided a selector circuit on the output side of the source data register, which selector circuit operates to deliver the data on the high-order side and that on the low-order side from the source data register selectively to the ALU on the high-order side and that on the low-order side according to the operating mode. Carry outputs from each of the ALUs are input to a first selector and one is selected according to the operating mode and stored in a carry flag register. The output of the carry flag register and the carry output of the ALU on the low-order side are input to a second selector whereby one output thereof is selected according to the operating mode and input to the ALU on the high-order side as the carry input thereto, and also, the output of the carry flag register is supplied to the ALU on the low-order side as the carry input thereto.