Input protection device for C-MOS device

摘要

An input protection device for a C-MOS device having an n-type semiconductor substrate and a p-type well region. The device comprises a diode consisting of the p-type well region and an n+-type layer diffusion formed in the p-type well region and connected between a gate of a C-MOS FET and ground. The n+-type layer of the diode has a higher impurity concentration and a greater diffusion depth than those of n+-type layers formed in the p-type well region and constitute the source and drain of an n-channel MOSFET.