| 摘要 |
The memory controller is connected to a MRQ of B-processor (1) connected to AND4, AND7 and AND8, a AIDLE of A-processor (2) connected to AND4 and AND11, a SYSRST connected to AND7-11, FF1, FF2, RST1 and RST2 and SYSCLK connected to FF1 and FF2. An input of decoder (3) is connected to the outputs of FF1 and FF2 (31,32). The outputs of decoder (11,12) are connected to OR1 and EN4. When two processors (A,B) need a memory access, the main processor obtains a memory access. When the main processor does not want the memory access, the other processor obtains the memory access.
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