发明名称 DIGITAL PHASE LOCKED LOOP OSCILLATOR
摘要 PURPOSE:To widen the pull-in range of a frequency compared to a conventional one even if the frequency-division rate of a reversible counter for suppressing a jitter is increased by adding and connecting a frequency control part between the reversible counter and a variable frequency-divider. CONSTITUTION:When the phase delay of an output signal continuously occurs, for example, the counting result of the reversible counter 11 is reduced in the frequency control part 6 and the frequency-division rate of the frequency divider 13 is correspondingly reduced. Consequently, the frequency of the phase forward shift of the output signal is increased, and it follows the phase of the input signal. When the phase of the output signal is in a locked state, the counting result of the reversible counter 11 holds a value at the time of locking for a prescribed period, whereby the frequency of the output signal is held to the value at the time of locking for the prescribed period. A mobile frequency follows the value at the time of locking so as to be changed. The pull-in range of the frequency is prevented from coming narrow even if the frequency-division rate of the counter 2 for suppressing the jitter is increased.
申请公布号 JPH01243620(A) 申请公布日期 1989.09.28
申请号 JP19880071394 申请日期 1988.03.24
申请人 NEC CORP 发明人 KOYAMA TORU
分类号 H03L7/06 主分类号 H03L7/06
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