NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE:To realize a high reliability, high readout speed E<2>PROM with less readout error by utilizing an erasing gate as a source wiring for reading data. CONSTITUTION:A NAND cell is constructed by serially connecting four memory cells M1-M4 to share their sources and drains. A selection transistor S is provided on the source of the one NAND cell. The memory cells M1-M4 having floating gates 41-44, and control gates 61-64. An erasing gate 11 is capacitively coupled with the floating gates 41-44 of each cell, and arranged to extend in a direction of cell arrangement. A memory array is constructed by permitting such NAND cells to be arranged into a matrix. A drain of the NAND cell is connected to a bit line BL. The control gates 61-64 of each memory cell is connected to a word line WL intersecting the bit line.