| 摘要 |
<p>A memory cell is provided comprising a bistable latch (I1, I2) having first and second nodes (NODE 1, NODE 2) and a nonvolatile transistor (NV1). The control gate of the nonvolatile transistor is connected to the first node and either the source or drain is connected to the second node. Means are provided for maintaining the control gate and the substrate of the transistor at substantially the same potential during volatile operation of the latch, thereby to reduce voltage stress which would lead to charge tunnelling to or from the floating gate. In this way, disturbance of the floating gate charge is avoided during volatile operation. The cell is particularly suited to silicon gate fabrication technology.</p> |
