Continuously variable clock delay circuit.

摘要

A clock-delay circuit for a sinusoidal clock output includes a pair of current amplifiers (12, 14), each connected to the clock output, wherein one of the amplifiers generates an amplified signal in phase with the clock output and the other generates a signal shifted in phase by 90 DEG . Both signals are multipled by control signals (ICZ, ICN) to alter their respective amplitudes prior to summation of both multiplier outputs. The sum of the multiplier outputs will be a sinusoidal waveform whose phase depends upon the control currents in the multipliers (16, 18) which are set by the user. Thus, the circuit provides a user-controlled continuously variable delay for a sinusoidal clock.