| 摘要 |
PURPOSE:To reduce the quantity of the accumulated electric charges of a PNP load memory cell when the cell is selected and making the inverting speed of the cell at the time of writing faster by adding a resistance to the cell. CONSTITUTION:A memory cell is constituted of PNP transistors Q1 and Q2, NPN transistors Q3-Q6, and resistances R1 and R2. When the memory cell is in a selected state, a readout current flows through the emitter of the transistor Q3. Therefore, saturation of the NPN transistor Q3 is accelerated and the base current of the transistor Q3 increases as compared with a case where the resistance R1 does not exist. Since the increase in the base current of the transistor Q3 increases the collector current of the PNP transistor Q1, saturation of the transistor Q1 is reduced. As a result, the inverting time of the memory cell can be made shorter. |
