发明名称 PATH TRACE VITERBI DECODER
摘要 <p>PATH TRACE VITERBI DECODER A path trace viterbi decoder comprising an ACS circuit for generating a path selecting signal, a path memory for storing the path selecting signal, a node calculator for calculating the node number of a most memory for storing the path selecting signal, a node calculator for calculating the node number of a most likely path on the basis of the data read out from the path memory, and a trace memory for storing the most likely path data, etc. The node number data of the most likely path calculated by the node calculator is stored in the trace memory and the decoding operation is carried out by using the data read from the trace memory.</p>
申请公布号 CA1260143(A) 申请公布日期 1989.09.26
申请号 CA19870530386 申请日期 1987.02.23
申请人 FUJITSU LIMITED 发明人
分类号 H03M13/41 主分类号 H03M13/41
代理机构 代理人
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