| 摘要 |
PURPOSE:To apply a fast test pattern without bit errors to a DUT, by performing a parity checking at a stage of sending a test pattern written into a low speed memory to the DUT through a high-speed memory. CONSTITUTION:A test pattern is transferred to a high-speed memory 4 through a low-speed memory 2 from a test pattern generator 1 and a parity detector 15 is provided at a stage of sending it to a DUT 5 to feed a detection output to a comparator circuit 16. On the other hand, parity of the test pattern from the test pattern 1 is detected with a parity detector 11 and transferred to a high-speed memory 14 through the low-speed memory 12 to compare an output thereof with an output of the parity detector 15 by the comparator circuit 16. The low-speed memories 2 and 12 and the high-speed memories 4 and 14 are accessed with counters 6 and 7 synchronously. This enables the applying of a fast test pattern without bit errors to the DUT. |
