| 摘要 |
A single diagonal syndrome generator receives first (forward reading) and second (reverse reading) sets of eight-bit data and a single vertical syndrome generator receives the first and second sets of eight-bit data from a progammable read only memory. The second set of data is reversed in bit order prior to delivery to the syndrome generators. The output of the two syndrome generators are delivered into an error processor and an error correction circuit for correcting errors in the first and second sets of eight-bit data. Upon error correction, the second set of eight-bit data is again reversed to put it in the same bit order as originally read.
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