| 摘要 |
<p>PURPOSE:To reproduce a clock without generating a phase error by mutually comparing two impulse responses obtained by sampling twice in a prescribed period and controlling the phase of a reproduced clock by this comparison result. CONSTITUTION:The discrimination result of a reception data symbol is detected from the output of a line equalizer 1 by a discrimination circuit 3, simultaneously a sample value is detected by a sample circuit 2 and an impulse response h(t1) in the vicinity of the peak value of the impulse response of a line equalizer output and an impulse response h(t2) delayed by a prescribed time from this impulse response h(t2) are respectively operated in each specific period from the detection result by an impulse response operation circuit 4. The h(t1) and the h(t2) are compared by a comparison circuit 5 and a control to advance the phase of a reproduction clock when the h(t1) is larger than the h(t) and to delay the phase of the reproduction clock when the h(t1) is smaller than the h(t2) is executed based on this comparison result by a clock control decision circuit 6.</p> |
