发明名称 COMPUTER SYSTEM WITH SUB PROCESSOR FOR FLOATING POINT COMPUTATION
摘要 PURPOSE:To detect the abnormality of a sub processor without fail, to process the sub processor with a main processor and to improve the reliability of a system by providing a floating point arithmetic procedure which executes floating point arithmetic with the main processor, in a storage device constituting the computer system. CONSTITUTION:The computer system is composed of a main processor 101, a sub processor 102, a storage device 103 and a switching device 104. Thus, when the system is tested, a power source is inputted and the system is activated. Then, the same floating point arithmetic as the sub processor 102 is executed by the main processor 101 and the arithmetic is compared. As the result of the comparison, when there is the abnormality in the sub processor 102, the main processor 101 switches a sub processor activating signal, which is originally inputted to the sub processor 102, to an interrupting signal to the main processor 101. After that, when a floating point arithmetic instruction appears, interruption is generated to the main processor 101 and the abnormality of the sub processor 102 is discovered without fail.
申请公布号 JPH01237720(A) 申请公布日期 1989.09.22
申请号 JP19880063384 申请日期 1988.03.18
申请人 HITACHI LTD 发明人 MUKAI HIROSHI;IKEGAWA MASAHIRO
分类号 G06F7/00 主分类号 G06F7/00
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