| 摘要 |
<p>PURPOSE:To increase the charging speed of a bit line and to execute the high speed of an access speed without enlarging a load transistor Tr of a sense amplifier by making the potential of a data bus into the intermediate level of a data 0 reading level and a data 1 reading level at the time of changing the address of a large capacity ROM. CONSTITUTION:Plural memory cells C00, C01... of a semiconductor device are arranged between plural word lines WL0, WL1... and plural bit lines BL0, BL1..., one of the lines BL0, BL1... and the lines WL0 and WL1... is selected in accordance with an address signal ADD (A0-A14) by selecting means 1-4 and the selected lines BL0, BL1... are connected to a data bus DB. The potential of the bus DB is detected by sensor amplifiers 5' and 5'' and an output voltage Dout is outputted in accordance with the potential. A signal changing circuit 7 detects the change of the bus DB, a pulse signal ATD and the inverse of ATD of a prescribed time width are generated, the amplifiers 5' and 5'' control the potential of the bus DB to the intermediate level of a 0 reading level and a 1 reading level in accordance with the signals ATD and the inverse of ATD.</p> |
