| 摘要 |
<p>PURPOSE:To attain the processing of a real time in a short detection time with simple circuit by detecting number of invalid data and generating a pulse having a time width corresponding to the invalid number, giving the result to a counter, deciding the result in addition in the clock and operating the sum of the counted number. CONSTITUTION:An output of an ineffective detection section 1 is fed to an LD of a counter 3, counted by a clock and a gate pulse decided by the number of ineffective data from a terminal Q is outputted, it is counted by an Ff 5 and the result is given to a terminal D of an adder section 6. The output of an FF 4 latches the final data of a data block. When all blocks are effective numbers, the number is '0' and in other cases, the value is 1. Thus, the output of the adder section 6 is an output being the sum of (k-1) being the output of the FF 5 and sum of '1's being an output of the Ff4.</p> |
