| 摘要 |
<p>A circuit implementing a block matching algorithm for coding video signals is disclosed. The circuit may be formed as a single VLSI chip. A VLSI chip implementing the block matching algorithm includes input means (110, 120, 122) which receive data sequentially (PE0 - PE16) so that the chip is a relatively small size, but also includes parallel processors so that the chip is fast.</p> |
