| 摘要 |
<p>PURPOSE:To easily set the operating speed of the title computer after reset is released in a test mode by automatically selecting specific timing from plural timing inputs when reset is made in a prescribed mode. CONSTITUTION:When a mode signal 14 is set to a 'H' level at the time of a test mode, a flip-flop 6 for control is not set irrespective of the level of an option signal 8. When reset is performed and a reset signal 9 becomes an 'H' level, the flip-flop 6 is reset and an output Q and timing controlling signal line 7 become 'L' in level. Assuming that a timing changeover circuit 4 selects a timing input terminal 3 for low speed when the signal line 7 is 'H' level and another timing input terminal 2 for high speed when the signal line 7 is 'L' level, the timing input terminal 2 for high speed is selected and an internal synchronizing signal 5 is inputted to an internal circuit 1 and the circuit 1 operates at high speed, since the control signal line 7 is 'L' in level.</p> |
