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发明名称
FAULT SIMULATION METHOD FOR INTEGRATED CIRCUIT
摘要
申请公布号
JPH01235872(A)
申请公布日期
1989.09.20
申请号
JP19880061863
申请日期
1988.03.17
申请人
TOSHIBA CORP
发明人
HIRABAYASHI KANJI
分类号
G01R31/28;G06F17/50;H01L21/66;H01L21/822;H01L27/04
主分类号
G01R31/28
代理机构
代理人
主权项
地址
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