| 摘要 |
<p>A semiconductor memory device includes a plurality of semiconductor pillar projections (3a, 3b) separated by grooves (4) formed in longitudinal and transverse directions in a substrate (1) and arranged in a matrix manner, a MOS capacitor (6, 7, 8) and a MOSFET (16, 2, 6, 11, 12a, 12b) formed on side surfaces at lower and upper portions, respectively, of each pillar projection (3a, 3b), a diffusion layer (16) of a source or drain of each MOSFET formed on an upper end face of the pillar projection (3a, 3b), and a bit line (17a) connected to the diffusion layer (16). The bit line (17a) is in contact with the upper end face of the pillar projection (3a, 3b) in a self-alignment manner.</p> |
