发明名称 Semiconductor wafer fabrication with improved control of internal gettering sites using RTA
摘要 The concentration of internal gettering sites within a semiconductor wafer is controlled by two-step thermal processing. In a concentration reduction phase, the wafer is rapidly heated to an elevated temperature in the range from about 900 DEG to 1350 DEG C., resulting in the partial or total dissolution of precipitable impurities within the wafer. In a concentration enhancement step, the wafers are subjected to a relatively low temperature anneal process where the density of potential internal gettering sites is increased. By properly controlling the processing temperatures and treatment times, the two steps may be performed in either order to obtain wafers having internal gettering site concentrations within a desired range.
申请公布号 US4868133(A) 申请公布日期 1989.09.19
申请号 US19890324858 申请日期 1989.03.16
申请人 DNS ELECTRONIC MATERIALS, INC. 发明人 HUBER, WALTER
分类号 H01L21/322 主分类号 H01L21/322
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