| 摘要 |
PURPOSE:To prevent multiple speed lock, by clearing a counter when it is detected that a motor is rotating with a speed higher than a reference speed based on a count in a counter and a FG pulse. CONSTITUTION:A trigger pulse generator 12 responds to a FG pulse and provides trigger pulses alternately to RSFF28, 40 as set inputs. The RSFF28, 40 are reset by count-up signals fed from counters 38, 46 for counting a reference clock. A discrete output circuit 6 outputs a faste signal or a slow signal based on the time width of counter reset signals fed from the RSFF28, 40. When 4/3 time speed detection circuits 56, 58 detect that a motor is rotating with a speed higher than 4/3 of a reference speed based on counts of the counters 38, 46 and the FG pulse, they provide clear pulses to the counters 38, 46. |
