| 摘要 |
<p>A method and circuit employ digital techniques in processing an input signal of a first frequency to develop an output signal of a second frequency that is a multiple of the first frequency. During each cycle of the input signal, a presettable down counter is decremented from its maximum value at a rate of 1/T1. The digital word appearing at the output of the down counter at the end of the cycle is programmed into an up counter that is clocked at a rate of 1/T2. The frequency of the signal developed at the overflow output of the up counter is divided by two by a flip-flop whose output provides a signal of a frequency which is T1/2T2 times that of the input signal. The frequency of the output signal changes after one cycle of a change in frequency of the input signal. The frequency multiplication factor can be a noninteger value.</p> |
