| 摘要 |
<p>An apparatus controls the movement of a data block between a peripheral and a data processing system, which comprises a bus which includes an address bus, a first data bus, and a second data bus, the peripheral being connected to the second data bus. A first memory, connected to the second data bus, stores data, and a second memory, connected to the first data bus, stores a plurality of dummy routines in predetermined areas, the predetermined areas of the second memory having corresponding buffer areas in the first memory. The first memory and the second memory correspond to a first memory area and a second memory area within a total predefined memory pace, each memory location within the total memory space being defined by a unique memory space address. A processor connected to the first data bus, fetches an instruction, in response to a control signal from the peripheral, from a preselected one of the dummy routines. The address of the instruction is placed on the address bus specifying a corresponding location of the corresponding buffer area in the first memory. A switch element connected to the first data bus and the second data bus, disconnects the first data bus from the second data bus in response to an enable signal. Logic circuitry generates at least one control signal in response to the fetching of the instruction from one of the dummy routines, such that data is transmitted between the peripheral and the data processing system.</p> |
