| 摘要 |
<p>PURPOSE:To improve the ultra-high frequency characteristics of a GaAs-FET by access or a contact by forming a structure in which a ground wiring layer for preventing charge-up is not formed in regions corresponding to the extending regions of wires connected to chips obtained by parting a wafer. CONSTITUTION:Ground wiring layers 6 are formed to parting line 2 sections along the longitudinal direction in parting lines 2 shaped to a latticed form. One parts of the ground wiring layers 6 are shaped to leading-out sections 16 extending in the cross direction at the centers of each chip 3, and unified respectively with the ground wiring layers 6 extending along the longitudinal direction. One parts of internal regions in the leading-out sections 16 are used as electron-beam drawing predetermined regions 4. When a wafer 1 is parted by the parting lines 2 into the chips 3, a wire 13 connected to a gate electrode or a drain electrode is stretched so as to cross on the edges of the chips 3, to which the ground wiring layers 6 are not shaped, in the wafer 1. Accordingly, since distances among the ground wiring layers 6 and an assembling wire can be taken sufficiently, an oscillation phenomenon due to electromagnetic induction among the wire 13 and the ground wiring layers 6 in an ultra-high frequency region can be prevented.</p> |
