| 摘要 |
PURPOSE:To constitute a VTR where the editing efficiency is good and a clock frequency is generated with a simple circuit, by setting the sampling frequency of a sound signal to an integer-fold horizontal scanning frequency. CONSTITUTION:Bit clocks for digital signal processing are inputted to an input terminal 24 by a clock generating circuit 34. Meanwhile, a vertical synchronizing signal separated in an integration circuit 18 is inputted to an input terminal 25, and a signal whose polarity is inverted at a field period is generated in a flip- flop 26. A signal whose phase is inverted at a frame period is generated from the output of the flip-flop 26 by a frequency divider 27 having division ratio 2. An exclusive OR between outputs of the flip-flop 26 and the frequency divider 27 is operated in an exclusive OR gate 28 to obtain a phase control signal (a). Bit clocks have the phase controlled in an EX-OR 29 by the phase control signal (a) to become clocks having a low disturbance degree and are outputted from an output terminal 30 and are used in a digital circuit shown in figure. The other output of the frequency divider 27 is outputted from an output terminal 31 and is mixed as a flag signal with a PCM signal and is recorded. |
