| 摘要 |
<p>In a phase perturbation compensation system for use in a data modem receiver, the signal from an equalizer (114) is fed to a phase and amplitude correction circuit (150) which is connected to a decision circuit (122) providing a data output signal (124) and a phase error output signal (120d) which is applied to a phase jitter compensation determination circuit (156). The phase jitter compensation determination circuit (156) includes a tapped delay line (269) the output taps of which are applied to multipliers (272-1 to 272-16) fed with adaptive weighting coefficients to provide values which are summed to provide a phase error prediction signal. The weighting coefficients are generated in integrator circuits (274-1 to 274-16) which include respective delays (288-1 to 288-16). The values generated in the delays (288-1 to 288-16) during an initial training sequence and stored in a storage device (130) are retrieved for use in subsequent training segments, whereby fast phase jitter adaptation is achieved and hence short training sequences can be utilized.</p> |
