发明名称 MICRO PROCESSOR WITH DECIMAL MULTIPLIER
摘要 <p>PURPOSE:To directly execute the multiplication of the multiplicand data of an integer and multiplier data of a decimal by providing a multiplication control block which sets an arithmetic logical operation means to add data in which a previous addition result is shifted right to multiplicand data. CONSTITUTION:In a micro processor having a decimal multiplier, a multiplication control circuit 41 consisting of a decoder 34 and a bit AND circuit 31 discriminates values for the bits of multiplicand data supplied through a data bus 10 by the signal of a multiplication control circuit 35 and the multiplication control block 30 which drives a switch group 32 by said result and which sets an arithmetic logical operation unit ALU 20 to add data in which the previous addition result is shifted right 33 to multiplicand data supplied from the bus 10 is provided. With such a constitution, multiplicand data of the integer and multiplication data can directly be added and an execution speed can be made faster than a multiplier which deals only integers.</p>
申请公布号 JPH01229322(A) 申请公布日期 1989.09.13
申请号 JP19880055181 申请日期 1988.03.09
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MIZUGUCHI HIROSHI;KUNIHIRA TADASHI;OTA YUTAKA;SAKAI TOSHIHIKO
分类号 G06F7/527;G06F7/52;G06F7/525;G06F7/53;G06F15/78;G06F17/10 主分类号 G06F7/527
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