LOGICAL SIMULATION METHOD AND LOGICAL SIMULATION DEVICE

摘要

PURPOSE:To efficiently execute the timing verification of a logical circuit including a wiring delay by adding each wiring delay time to the vent time of an event to hold each wiring delay time in a logical circuit which is made into a simulation object with an event communicating part and to display the signal condition change of respective elements at an output terminal. CONSTITUTION:An event to display the signal condition change of the input terminal of a logical element is evaluated, the action delay time of the element is added and an event to display the signal condition change of the output terminal of the logical element is calculated (evaluation processing). To the event time of the event calculated by the evaluation processing, the delaying time of respective wirings is added by using a wiring delaying time storing part 223 and a wiring delaying time adding part 224, the event to display the signal condition change of the input terminal of the logical element connected to the output terminal is newly calculated and communicated to an input terminal. The evaluatable event is determined and extracted from the communicated event group. Thus, the timing verification of the logical circuit including a wiring delay can be efficiently executed.